Recently, in a manufacturing process of a semiconductor device, damascene wirings or buried wirings are often fabricated by forming a metal film on an insulating film having trenches thereon such that the trenches are filled with the material of the metal film and by polishing the metal film by using the CMP method.
FIG. 4A through FIG. 4C are schematic cross sectional views illustrating a conventional method of polishing a metal film to form such a damascene wiring.
In this method, as shown in FIG. 4A, a groove or a trench 33 is formed in an insulating film 32, such as an oxide film and the like, formed on a semiconductor substrate 31 by using photolithography and etching, and the like. In the drawings, only one trench is shown for the sake of simplicity. However, in practice, it is possible to form many trenches and, therefore, many damascene wirings simultaneously. Then, as shown in FIG. 4B, a metal film 36 is formed on the insulating film 32 such that the trench 33 is filled with the material of the metal film 36. Thereafter, as shown in FIG. 4C, the metal film 36 is polished by the CMP method until the insulating film 32 is exposed. Thereby, a buried wiring, that is, the damascene wiring 37, which comprises a portion of the metal film 36 remaining in the trench 33 is formed.
However, in the above-mentioned conventional method, as the width of the trench 33 becomes large, the portion of the metal film 36 buried in the trench 33 is overpolished in the vicinity of the central portion of the trench 33. Thereby, as shown in FIG. 4C, a recessed portion is produced on the upper surface of the damascene wiring 37.
Japanese patent laid-open publication No. 9-8039 discloses a method of forming a buried wiring which can improve the disadvantage of the above-mentioned conventional method of forming a damascene wiring.
FIG. 5A through FIG. 5C illustrate a method of forming a buried wiring disclosed in Japanese patent laid-open publication No. 9-8039. First, as shown in FIG. 5A, trenches 43 are formed in an insulating film 42 formed on a semiconductor substrate 41 by using photolithography and etching. In this case, island patterns 44 comprising portions of the insulating film 42 are left in the trenches 43.
Then, as shown in FIG. 5B, a metal film 45 is formed on the insulating film 42 such that the trenches 43 are filled by the material of the metal film 45. Thereafter, as shown in FIG. 5C, the metal film 45 is polished by the CMP method until the insulating film 42 is exposed. Thereby, a buried wiring, that is, a damascene wiring, 46 is formed in each of the trenches 43. By using this method, since the island patterns 44 exist in each of the trenches 43, it is possible to avoid overpolishing, that is, dishing, which occurs when a buried wiring pattern having large area is formed.
However, in the method disclosed in Japanese patent laid-open publication No. 9-8039 and described above, the volume of each buried wiring 46 decreases by the amount of the volume of the island patterns 44. Therefore, it is impossible to obtain good electrical characteristic, such as electrical resistance and the like, of the buried wiring 46. Also, because of the existence of the island patterns 44, there is a possibility that the electrical characteristic becomes even worse. Further, when the buried wiring 46 is to be coupled, for example, to any other conductor portion by using a via hole and the like, it is necessary to consider locations and sizes of the island patterns 44. Therefore, design of connection in a semiconductor device becomes complicated. These disadvantages are caused by forming the island patterns 44 in each of the trenches 43.